Leakage Current: Moore's Law Meets Static Power

P ower consumption is now the major technical problem facing the semiconductor industry. In comments on this problem at the 2002 International Electron Devices Meeting, Intel chairman Andrew Grove cited off-state current leakage in particular as a limiting factor in future microprocessor integration. 1 Off-state leakage is static power, current that leaks through transistors even when they are turned off. It is one of two principal sources of power dis-sipation in today's microprocessors. The other is dynamic power, which arises from the repeated capacitance charge and discharge on the output of the hundreds of millions of gates in today's chips. Until very recently, only dynamic power has been a significant source of power consumption, and Moore's law has helped to control it. Shrinking processor technology has allowed and, below 100 nanometers, actually required reducing the supply voltage. Dynamic power is proportional to the square of supply voltage, so reducing the voltage significantly reduces power consumption. Unfortunately, smaller geometries exacerbate leakage , so static power begins to dominate the power consumption equation in microprocessor design. Historically, complementary metal-oxide semiconductor technology has dissipated much less power than earlier technologies such as transistor-transistor and emitter-coupled logic. In fact, when not switching, CMOS transistors lost negligible power. However, the power they consume has increased dramatically with increases in device speed and chip density. The research community has recognized the significance of this increase for some time. Figure 1 shows total chip dynamic and static power consumption trends based on 2002 statistics normalized to the 2001 International Technology Road-map for Semiconductors. 2 The ITRS projects a decrease in dynamic power per device over time. However, if we assume a doubling of on-chip devices every two years, total dynamic power will increase on a per-chip basis. Packaging and cooling costs as well as the limited power capacity of batteries make this trend unsustainable. Figure 1 also shows exponential increases projected for the two principal components of static power consumption: • subthreshold leakage, a weak inversion current across the device; and • gate leakage, a tunneling current through the gate oxide insulation. The ITRS expects the rate of these increases to level out in 2005 but to remain substantial nonetheless. Even today, total power dissipation from chip leakage is approaching the total from dynamic power, and the projected increases in off-state subthreshold leakage show it exceeding total dynamic power consumption as technology drops below the 65-nm feature …